The invention relates generally to integrated circuits and, in particular, to device structures involving a conductor-filled via or trench and methods of forming such device structures.
Through-silicon vias are short, vertical electrical connections that pass through a wafer to establish an electrical connection from the active device side to the backside of a die. Through-silicon vias improve spatial efficiencies and interconnect densities in comparison with wire bonding and flip chip stacking. A through-silicon via is fabricated by etching a via into the wafer and filling the resulting via with a conductor. The silicon wafer is thinned from its backside until the conductor fill is exposed, and backside metal is applied on the thinned backside surface to establish electrical contact. Through-silicon vias are an enabling technology for three-dimensional (3D) vertical integration for stacking die with a reduced form factor.
Device structures involving a conductor-filled via or trench and methods of forming such device structures are needed.